hypr_risc RISC-V-Based Radar Signal Processor

Fastest Solutions on the Market

The Fastest Radar Signal Processor.

What is hypr_risc?

hypr_risc is a radar hardware accelerator attached to a custom-generated RISC-V-based core. We achieve the highest possible DSP speed by generating the optimal solution for your application based on desired input and output parameters. hypr_risc is highly configurable to provide the best answer to performance, size, and power consumption requirements and limitations. Applicable to everything from small, low-power chips to high-performance multi-core application processors.

Benefits of hypr_risc

Low latency / high throughput

Energy Efficiency

Leading edge PPA

Satellite Architecture

Why RISC-V?

RISC-V is a free and open ISA (instruction set architecture) developed at UC Berkeley. It has a modular design, allowing users to add extensions to the base set of instructions depending on the project application.

By being free to use, RISC-V has facilitated innovation in processor research and development, enabling the creation of pioneering solutions for industries like automotive or IoT.

Advantages of RISC-V

Reduced development expenses – no royalties cost for ISA use
More Customization Options – allows for chipset hardware customization in terms of size and power usage
Faster Time To Market – reusing open-source IP speeds up development
Community Support – open-source community promotes collaboration and offers shared resources

How Does hypr_risc Work?

hypr_risc is built using a RISC-V-based core attached to a custom radar hardware accelerator.

The accelerator uses parameters like the number of transmitters and receivers as well as ADC characteristics as input and generates the optimal solution based on these metrics. hypr_risc is front-end agnostic and can be connected to any type of RF frontend regardless of the manufacturer.

hypr_risc can be configured to process information about object range, velocity, and angle. The output can be anything from a simple distance measurement to an imaging radar interface, depending on your application needs.

By generating a tailored solution for your needs, hypr_risc enables cost savings through optimized chip size and power usage, while ensuring the highest possible radar signal processing speed.

hypr_risc Advantages

High-Speed

Ultra-fast response time, critical for automotive industry applications where a quick reaction is paramount.

RF Front-end Agnostic

Front-end agnostic, can be connected to any major manufacturer’s or a custom-made RF frontend.

Highly-parameterizable

Fully customizable core generator based on all types of RISC-V processor cores. You can choose:

Single-core or multi-core setup
Core size (number of pipeline stages)
Cache size and levels, number of TLB entries
Bus types
Interrupt types and priority levels
Width of off-chip I/O
Other parameters

Optimized Performance

We optimize radar DSP performance based on your needs. Input parameters like the number of transmitters and receivers are used to generate the best solution in terms of chip size, performance, and power consumption. Outputs can be anything from simple parking sensor distance measurement to complex imaging radar applications.

Our Project in the Top 40 for Google-sponsored Efabless Open MPW Shuttle

Efabless Open MPW Shuttle is a Google-sponsored program providing fabrication for fully open-source projects using the SkyWater Open Source PDK (Process Design Kit).

A submission from NOVELIC/NIRSEN was chosen as one of the 40 successfully fabricated projects. Each design was made on Caravel, an SoC harness powered by PicoRV32, a RISC-V-based CPU core.

Our team designed Spectravel, a digital spectrometer SoC consisting of an SDF-FFT (Single-Path Delay-Feedback Fast Fourier Transform) generator and its support circuitry, written in Chisel.

The potential of full open-source lies in reusing hardware design for radar signal processing backend to increase development speed and productivity.